VHDL Tutorial

Generic constants  Parameterizing Behavior
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Parameterizing behavior

Parameterizing structure

Parameterizing Behavior

 

VHDL provides us with a mechanism, called generics, for writing parameterized mod- els.   We  can  write  a  generic  entity  by  including  a  generic list  in  its  declaration  that defines the formal generic constants that parameterize the entity.  The extended syn- tax rule for entity declarations including generics is

 

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entity_declaration

entity identifier is

[ generic ( generic_interface_list ) ; ]

[ port ( port_interface_list ) ; ]

end [ entity ] [ identifier ] ;

 

The generic interface list is like a parameter list, but with the restriction that we can only include constant-class objects, which must be of mode in Since these are the defaults for a generic list, we can use a simplified syntax rule:

 

generic_interface_list

( identifier { , } : subtype_indication [ := expression ] )

{ ; }

 

A simple example of an entity declaration including a generic interface list is

 

entity and2 is

generic ( Tpd : time );

port ( a, b : in bit;  y : out bit );

end entity and2;

 

This entity includes one generic constant, Tpd, of the predefined type time.  The value

of this generic constant may be used within the entity statements and any architecture body  corresponding  to  the  entity.   In  this  example  the  intention  is  that  the  generic constant specify the propagation delay for the module, so the value should be used

in a signal assignment statement as the delay.   An architecture body that does this is

 

architecture simple of and2 is begin    

 

and2_function :

y <= a and b after Tpd;

end architecture simple;

 

A generic constant is given an actual value when the entity is used in a component instantiation statement.   We do this by including a generic map, as shown by the ex- tended syntax rule for component instantiations:

 

component_instantiation_statement

instantiation_label :

entity entity_name ( architecture_identifier )

[ generic map ( generic_association_list ) ]

port map ( port_association_list ) ;

 

The generic association list is like other forms of association lists, but since gener-

ic constants are always of class constant, the actual arguments we supply must be ex- pressions.   Thus the simplified syntax rule for a generic association list is

 

generic_association_list

( [ generic_name => ] ( expression I open ) ) { , }

 

To illustrate this, let us look at a component instantiation statement that uses the

and2 entity shown above:

 

gate1 : entity work.and2(simple)

generic map ( Tpd => 2 ns )

port map ( a => sig1,  b => sig2,  y => sig_out );

 

The  generic  map  specifies  that  this  instance  of  the  and2  module  uses  the  value

2 ns for the generic constant Tpd; that is, the instance has a propagation delay of 2 ns. We might include another component instantiation statement using and2 in the same design but with a different actual value for Tpd in its generic map, for example:

 

gate2 : entity work.and2(simple)

generic map ( Tpd => 3 ns )

port map ( a => a1,  b => b1,  y => sig1 );

 

When the design is elaborated we have two processes, one corresponding to the in- stance gate1 of and2, which uses the value 2 ns for Tpd, and another corresponding

to the instance gate2 of and2, which uses the value 3 ns.

 

 

 

 

 

 

 

 

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