VHDL Tutorial

Fundamental concepts
Modelling concepts
Elements of behaviour
Elements of structure
Analysis elaboration
Lexical elements

Characters and strings 
Syntax descriptions
Constants and variables
Scalar type
Integer types
Floating point types
Time type
Enumeration types
Character types
Boolean type 
Bits type
Standard logic
Sequential statements
Case statements
Loop and exit statements
Assertion statements
Array types & array operations
Architecture bodies
Entity declarations
Behavioral descriptions 
Wait statements
Delta delays
Process statements
Conditional signal assignment 
Selected signal assigment
Structural descriptions
Library and library clauses
Procedure parameters
Signal parameters
Default values
Unconstrained array parameter
Package declarations and bodies
Subprograms in package
Use clauses
Resolved signals and subtypes
Resolved signals and ports
Parameterizing behavior
Parameterizing structure




Identifiers are used to name items in a VHDL model.   An identifier


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 may only contain alphabetic letters (A to Z and a to z), decimal digits (0

to 9) and the underline character (_);


 must start with an alphabetic letter;


 may not end with an underline character; and


 may not include two successive underline characters.


Case of letters is not significant.   Some examples of valid basic identifiers are


A    X0    counter    Next_Value    generate_read_cycle


Some examples of invalid basic identifiers are


last@value       contains an illegal character for an identifier

5bit_counter    starts with a nonalphabetic character

_A0                  starts with an underline

A0_                  ends with an underline

clock__pulse    two successive underlines