VHDL Tutorial

Package Declarations and bodies
Introduction
Fundamental concepts
Modelling concepts
Elements of behaviour
Elements of structure
Analysis elaboration
Lexical elements
Identifiers
Numbers
Characters and strings 
Syntax descriptions
Constants and variables
Scalar type
Integer types
Floating point types
Time type
Enumeration types
Character types
Boolean type 
Bits type
Standard logic
Sequential statements
Case statements
Loop and exit statements
Assertion statements
Array types & array operations
Architecture bodies
Entity declarations
Behavioral descriptions 
Wait statements
Delta delays
Process statements
Conditional signal assignment 
Selected signal assigment
Structural descriptions
Library and library clauses
Procedures
Procedure parameters
Signal parameters
Default values
Unconstrained array parameter
Functions
Package declarations and bodies

Subprograms in package
Use clauses
Resolved signals and subtypes
Resolved signals and ports
Parameterizing behavior
Parameterizing structure

Package Declarations and Bodies

 

A VHDL package is simply a way of grouping a collection of related declarations that serve a common purpose.   They allow us to separate the external view of the items they declare from the implementation of those items.   The external view is specified

in a package declaration, whereas the implementation is defined in a separate pack- age body The syntax rule for writing a package declaration is

 

package_declaration

package identifier is

{ package_declarative_item }

end [ package ] [ identifier ] ;

 

The identifier provides a name for the package, which we can use elsewhere in

a model to refer to the package.  Inside the package declaration we write a collection

of  declarations,  including  type,  subtype,  constant,  signal  and  subprogram  declara- tions.    These  are  the  declarations  that  are  provided  to  the  users  of  the  package. Figure 6-1 is a simple example of a package declaration.

 

FIGURE 6-1

 

package cpu_types is

constant word_size : positive := 16;

constant address_size : positive := 24;

subtype word is bit_vector(word_size 1 downto 0);

subtype address is bit_vector(address_size 1 downto 0);

type status_value is ( halted, idle, fetch, mem_read, mem_write, io_read, io_write, int_ack );

end package cpu_types;

 

A package that declares some useful constants and types for a CPU model.

 

A package is another form of design unit, along with entity declarations and ar- chitecture bodies.   It is separately analyzed and is placed into the working library as

a library unit by the analyzer.  From there, other library units can refer to an item de- clared  in  the  package  using  the  selected  name  of  the  item.    The  selected  name  is

 

formed by writing the library name, then the package name and then the name of the item, all separated by dots; for example:

 

work.cpu_types.status_value

 

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