VHDL Tutorial

Procedures in VHDL
Introduction
Fundamental concepts
Modelling concepts
Elements of behaviour
Elements of structure
Analysis elaboration
Lexical elements
Identifiers
Numbers
Characters and strings 
Syntax descriptions
Constants and variables
Scalar type
Integer types
Floating point types
Time type
Enumeration types
Character types
Boolean type 
Bits type
Standard logic
Sequential statements
Case statements
Loop and exit statements
Assertion statements
Array types & array operations
Architecture bodies
Entity declarations
Behavioral descriptions 
Wait statements
Delta delays
Process statements
Conditional signal assignment 
Selected signal assigment
Structural descriptions
Library and library clauses
Procedures

Procedure parameters
Signal parameters
Default values
Unconstrained array parameter
Functions
Package declarations and bodies
Subprograms in package
Use clauses
Resolved signals and subtypes
Resolved signals and ports
Parameterizing behavior
Parameterizing structure


Procedures

 

We start our discussion of subprograms with procedures There are two aspects to using procedures in a model: first the procedure is declared, then elsewhere the pro- cedure is called The syntax rule for a procedure declaration is

 

subprogram_body

procedure identifier [ ( parameter_interface_list ) ] is

{ subprogram_declarative_part }

begin

{ sequential_statement }

end [ procedure ] [ identifier ] ;

 

For now we will just look at procedures without the parameter list part; we will come back to parameters in the next section.

The identifier in a procedure declaration names the procedure The name may be repeated at the end of the procedure declaration.  The sequential statements in the body of a procedure implement the algorithm that the procedure is to perform  and can include any of the sequential statements that we have seen in previous chapters.

A procedure can declare items in its declarative part for use in the statements in the procedure  body.   The  declarations  can  include  types,  subtypes, constants, variables and nested subprogram declarations.   The items declared are not accessible outside

of the procedure; we say they are local to the procedure.

The actions of a procedure are invoked by a procedure call statement, which is yet  another  VHDL  sequential  statement.   A  procedure  with  no  parameters  is  called simply by writing its name, as shown by the syntax rule

 

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procedure_call_statement procedure_name ;

 

When the last statement in the procedure is completed, the procedure returns.

We  can  write  a  procedure  declaration  in  the  declarative  part  of  an  architecture body  or  a  process.   If  a  procedure  is  included  in  an  architecture  body’s  declarative part, it can be called from within any of the processes in the architecture body.   On the other hand, declaring a procedure within a process hides it away from use by other processes.

 

EXAMPLE

 

The outline in Figure 5-1 illustrates a procedure for arithmetic operations de- fined within a process.  The process alu invokes do_arith_op with a procedure call statement.

 

FIGURE 5-1

 

architecture rtl of control_processor is

type func_code is (add, subtract);

signal op1, op2, dest : integer;

signal Z_flag : boolean;

signal func : func_code;

…

begin

alu : process is

procedure do_arith_op is variable result : integer;

begin

case func is

when add =>

result := op1 + op2;

when subtract =>

result := op1 – op2;

end case;

dest  <=  result after Tpd;

Z_flag  <=  result = 0 after Tpd;

end procedure do_arith_op;

begin

…

do_arith_op;

…

end process alu;

…

end architecture rtl;

 

An outline of an architecture body with a process containing a procedure.  The procedure encapsulates

part of the behavior of the process and is invoked by the procedure call statement within the process.

 

 

 

 

 

 

 

 

 

 

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