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VHDL Tutorial |
Scalar type in VHDL | ||
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Introduction Fundamental concepts Modelling concepts Elements of behaviour Elements of structure Analysis elaboration Lexical elements Identifiers Numbers Characters and strings Syntax descriptions Constants and variables Scalar type Integer types Floating point types Time type Enumeration types Character types Boolean type Bits type Standard logic Sequential statements Case statements Loop and exit statements Assertion statements Array types & array operations Architecture bodies Entity declarations Behavioral descriptions Wait statements Delta delays Process statements Conditional signal assignment Selected signal assigment Structural descriptions Library and library clauses Procedures Procedure parameters Signal parameters Default values Unconstrained array parameter Functions Package declarations and bodies Subprograms in package Use clauses Resolved signals and subtypes Resolved signals and ports Parameterizing behavior Parameterizing structure |
. Scalar Types
A scalar type is one whose values are indivisible. In this section, we review VHDL’s predefined scalar types. We will also show how to define new enumeration types.
Subtypes
In many models, we want to declare objects that should only take on a restricted range of values. We do so by first declaring a subtype, which defines a restricted set of val- ues from a base type. The simplified syntax rules for a subtype declaration are
subtype_declaration ⇐ subtype identifier is subtype_indication ; subtype_indication ⇐ type_mark range simple_expression ( to I downto ) simple_expression
We will look at other forms of subtype indications later. The subtype declaration defines the identifier as a subtype of the base type specified by the type mark, with the range constraint restricting the values for the subtype.
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