VHDL Tutorial

Sequential statements in VHDL
Fundamental concepts
Modelling concepts
Elements of behaviour
Elements of structure
Analysis elaboration
Lexical elements
Characters and strings 
Syntax descriptions
Constants and variables
Scalar type
Integer types
Floating point types
Time type
Enumeration types
Character types
Boolean type 
Bits type
Standard logic
Sequential statements

Case statements
Loop and exit statements
Assertion statements
Array types & array operations
Architecture bodies
Entity declarations
Behavioral descriptions 
Wait statements
Delta delays
Process statements
Conditional signal assignment 
Selected signal assigment
Structural descriptions
Library and library clauses
Procedure parameters
Signal parameters
Default values
Unconstrained array parameter
Package declarations and bodies
Subprograms in package
Use clauses
Resolved signals and subtypes
Resolved signals and ports
Parameterizing behavior
Parameterizing structure

Sequential Statements


In this section we look at how data may be manipulated within processes using se- quential statements, so called because they are executed in sequence We have al- ready seen one of the basic sequential statements, the variable assignment statement. The statements we look at in this section deal with controlling actions within a model; hence they are often called control structures.  They allow selection between alterna- tive courses of action as well as repetition of actions.


If Statements


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In  many  models,  the  behavior  depends  on  a  set  of conditions  that  may  or  may  not hold true during the course of simulation.  We can use an if statement to express this behavior The syntax rule for an if statement is



[ if_label : ]

if boolean_expression then

{ sequential_statement }

{ elsif boolean_expression then

{ sequential_statement } }

[ else 

{ sequential_statement } ]

end if [ if_label ] ;


A simple example of an if statement is


if en = '1' then

stored_value := data_in;

end if;


The Boolean expression after the keyword if is the condition that is used to con- trol whether or not the statement after the keyword then is executed.  If the condition evaluates to true, the statement is executed We can also specify actions to be per- formed if the condition is false.   For example:


if sel = 0 then

result <= input_0;     executed if sel = 0



result <= input_1;       executed if sel /= 0

end if;


Here,  as  the  comments  indicate,  the  first  signal  assignment  statement  is  executed  if the condition is true, and the second  signal  assignment statement is executed  if the condition is false.

We can construct a more elaborate form of if statement to to check a number of different conditions, for example:


if mode = immediate then

operand := immed_operand;

elsif opcode = load or opcode = add or opcode = subtract then

operand := memory_operand;


operand := address_operand;

end if;


In general, we can construct an if statement with any number of elsif clauses (in- cluding none), and we may include or omit the else clause.  Execution of the if state- ment  starts  by  evaluating  the  first  condition.   If  it  is  false,  successive  conditions  are evaluated,  in  order,  until  one  is  found  to  be  true,  in  which  case  the  corresponding statements are executed.   If none of the conditions is true, and we have included an else clause, the statements after the else keyword are executed.





A heater thermostat can be modeled as an entity with two integer inputs, one that  specifies  the  desired  temperature  

and  another  that  is  connected  to  a  ther- mometer, and one Boolean output that turns a heater on and off.  The thermostat turns the heater on if the measured temperature falls below two degrees less than the desired temperature, and turns the heater off if the measured temperature ris-

es above two degrees greater than the desired temperature.




Figure 3-3 shows the entity and architecture bodies for the thermostat.   The entity declaration defines the input and output ports The process in the archi- tecture body includes the input ports in the sensitivity list after the keyword proc- ess.  This is a list of signals to which the process is sensitive.  When any of these signals  changes  value,  the  process  resumes  and  executes  the  sequential  state- ments.  After it has executed the last statement, the process suspends again.  The

if  statement  compares  the  actual  temperature  with  the  desired  temperature  and turns the heater on or off as required.




entity thermostat is

port ( desired_temp, actual_temp : in integer;

heater_on : out boolean );

end entity thermostat;

architecture example of thermostat is begin

controller : process (desired_temp, actual_temp) is begin

if actual_temp < desired_temp 2 then

heater_on <= true;

elsif actual_temp > desired_temp + 2 then

heater_on <= false;

end if;

end process controller;

end architecture example;