VHDL Tutorial

Structural Descriptions in VHDL
Fundamental concepts
Modelling concepts
Elements of behaviour
Elements of structure
Analysis elaboration
Lexical elements
Characters and strings 
Syntax descriptions
Constants and variables
Scalar type
Integer types
Floating point types
Time type
Enumeration types
Character types
Boolean type 
Bits type
Standard logic
Sequential statements
Case statements
Loop and exit statements
Assertion statements
Array types & array operations
Architecture bodies
Entity declarations
Behavioral descriptions 
Wait statements
Delta delays
Process statements
Conditional signal assignment 
Selected signal assignment
Structural descriptions

Library and library clauses
Procedure parameters
Signal parameters
Default values
Unconstrained array parameter
Package declarations and bodies
Subprograms in package
Use clauses
Resolved signals and subtypes
Resolved signals and ports
Parameterizing behavior
Parameterizing structure

       Structural Descriptions


A structural description of a system is expressed in terms of subsystems interconnect- ed by signals.  Each subsystem may in turn be composed of an interconnection of sub- subsystems, and so on, until we finally reach a level consisting of primitive compo- nents, described purely in terms of their behavior.   Thus the top-level system can be thought of as having a hierarchical structure.  In this section, we look at how to write structural architecture bodies to express this hierarchical organization.


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Entity Instantiation and Port Maps


We have seen earlier in this chapter that the concurrent statements in an architecture body describe an implementation of an entity interface.  In order to write a structural implementation, we must use  a concurrent statement called a  component instantia- tion statement, the simplest form of which is governed by the syntax rule



instantiation_label :

entity entity_name ( architecture_identifier )

port map ( port_association_list ) ;


This form of component instantiation statement performs direct instantiation of an entity We can think of component instantiation as creating a copy of the named entity,  with  the  corresponding  architecture  body  substituted  for  the  component  instance.  The port map specifies which ports of the entity are connected to which sig- nals  in  the  enclosing  architecture  body.     The  simplified  syntax  rule  for  a  port association list is



( [ port_name => ] signal_name ) { , }


Each element in the association list associates a port of the entity with a signal of the enclosing architecture body.

Let us look at some examples to illustrate component instantiation statements and the association of ports with signals.   Suppose we have an entity declared as


entity DRAM_controller is

port ( rd, wr, mem : in bit;

ras, cas, we, ready : out bit  );

end entity DRAM_controller;


and a corresponding architecture called fpld.  We might create an instance of this entity as follows:


main_mem_controller : entity work.DRAM_controller(fpld)

port map ( cpu_rd, cpu_wr, cpu_mem,

mem_ras, mem_cas, mem_we, cpu_rdy );


In this example, the name work refers to the current working library in which en- tities and architecture bodies are stored.  We return to the topic of libraries in the next section.   The port map of this example lists the signals in the enclosing architecture body to which the ports of the copy of the entity are connected.   Positional associa- tion is used: each signal listed in the port map is connected to the port at the same position in the entity declaration.  So the signal cpu_rd is connected to the port rd, the signal cpu_wr is connected to the port wr and so on.

A better way of writing a component instantiation statement is to use named as- sociation, as shown in the following example:


main_mem_controller : entity work.DRAM_controller(fpld)

port map ( rd => cpu_rd, wr => cpu_wr,

mem => cpu_mem, ready => cpu_rdy,

ras => mem_ras, cas => mem_cas, we => mem_we );


Here, each port is explicitly named along with the signal to which it is connected.  The order in which the connections are listed is immaterial.




In Figure 4-2 we looked at a behavioral model of an edge-triggered flipflop. We can use the flipflop as the basis of a 4-bit edge-triggered register.   Figure 4-3 shows the entity declaration and a structural architecture body.




entity reg4 is

port ( clk, clr, d0, d1, d2, d3 : in bit;  q0, q1, q2, q3 : out bit );

end entity reg4;

architecture struct of reg4 is begin

bit0 : entity work.edge_triggered_Dff(behavioral)

port map (d0, clk, clr, q0);

bit1 : entity work.edge_triggered_Dff(behavioral)

port map (d1, clk, clr, q1);

bit2 : entity work.edge_triggered_Dff(behavioral)

port map (d2, clk, clr, q2);

bit3 : entity work.edge_triggered_Dff(behavioral)

port map (d3, clk, clr, q3);

end architecture struct;


An entity and structural architecture body for a 4-bit edge-triggered register, with an asynchronous

clear input.


We can use the register entity, along with other entities, as part of a structural architecture  for  the  two-digit  decimal  counter  represented  by  the  schematic  of Figure 4-4.

Suppose a digit is represented as a bit vector of length four, described by the subtype declaration


subtype digit is bit_vector(3 downto 0);


Figure 4-5 shows the entity declaration for the counter, along with an outline

of the structural architecture body.   This example illustrates a number of impor- tant points about component instances and port maps.  First, the two component instances val0_reg and val1_reg are both instances of the same entity/architecture pair.  This means that two distinct copies of the architecture struct of reg4 are cre- ated, one for each of the component instances.  We return to this point when we discuss the topic of elaboration in the next section Second, in each of the port maps, ports of the entity being instantiated are associated with separate elements

of array signals This is allowed, since a signal that is of a composite type, such

as an array, can be treated as a collection of signals, one per element.  Third, some

of the signals connected to the component instances are signals declared within the enclosing architecture body, registered, whereas the clk signal is a port of the entity counter.  This again illustrates the point that within an architecture body, the ports of the corresponding entity are treated as signals.




entity counter is

port ( clk, clr : in bit;

q0, q1 : out digit );

end entity counter;



architecture registered of counter is


signal current_val0, current_val1, next_val0, next_val1 : digit;


val0_reg : entity work.reg4(struct)

port map ( d0 => next_val0(0), d1 => next_val0(1), d2 => next_val0(2), d3 => next_val0(3),

q0 => current_val0(0), q1 => current_val0(1), q2 => current_val0(2), q3 => current_val0(3), clk => clk, clr => clr );

val1_reg : entity work.reg4(struct)

port map ( d0 => next_val1(0), d1 => next_val1(1), d2 => next_val1(2), d3 => next_val1(3),q0 => current_val1(0), q1 => current_val1(1), q2 => current_val1(2), q3 => current_val1(3), clk => clk, clr => clr );

incr0 : entity work.add_1(boolean_eqn) ;

incr1 : entity work.add_1(boolean_eqn) ;

buf0 : entity work.buf4(basic) ;

buf1 : entity work.buf4(basic) ;

end architecture registered;


An entity declaration of a two-digit decimal counter, with an outline of an architecture body using the

reg4 entity.