VHDL Tutorial

Time type in VHDL
Fundamental concepts
Modelling concepts
Elements of behaviour
Elements of structure
Analysis elaboration
Lexical elements
Characters and strings 
Syntax descriptions
Constants and variables
Scalar type
Integer types
Floating point types
Time type

Enumeration types
Character types
Boolean type 
Bits type
Standard logic
Sequential statements
Case statements
Loop and exit statements
Assertion statements
Array types & array operations
Architecture bodies
Entity declarations
Behavioral descriptions 
Wait statements
Delta delays
Process statements
Conditional signal assignment 
Selected signal assigment
Structural descriptions
Library and library clauses
Procedure parameters
Signal parameters
Default values
Unconstrained array parameter
Package declarations and bodies
Subprograms in package
Use clauses
Resolved signals and subtypes
Resolved signals and ports
Parameterizing behavior
Parameterizing structure



VHDL has a predefined type called time that is used to represent simulation times and delays.   We can write a time value as a numeric literal followed by a time unit.   For example:


5 ns    22 us    471.3 msec


Notice that we must include a space before the unit name.   The valid unit names are


fs    ps    ns    us    ms    sec    min    hr

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The type time includes both positive and negative values.  VHDL also has a rede- fined subtype of time, delay_length, that only includes non-negative values.

Many  of  the  arithmetic  operators  can  be  applied  to  time  values,  but  with  some restrictions.  The addition, subtraction, identity and negation operators can be applied

to yield results of type time A time value can be multiplied or divided by an integer

or real value to yield a time value, and two time values can be divided to yield an in- teger For example:


18 ns / 2.0  =  9 ns,    33 ns / 22 ps  =  1500


Finally, the abs operator may be applied to a time value, for example:


abs 2 ps  =  2 ps,    abs (2 ps)  =  2 ps