VHDL Tutorial

Use Clauses in VHDL
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Use Clauses


We have seen how we can refer to an item provided by a package by writing its se- lected name, for example, work.cpu_types.status_value This name refers to the item status_value in the package cpu_types stored in the library work If we need to refer to this object in many places in a model, having to write the library name and package name becomes tedious and can obscure the intent of the model.  We can write a use clause to make names from package directly visible The syntax rules are:


use_clause use selected_name { , } ;

selected_name identifier . identifier . ( identifier I all )


In one form of selected name, the first identifier is a library name and the second

is the name of a package within the library.   This form allows us to refer directly to items within a package without having to use the full selected name.   For example, we could write a use clause

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use work.cpu_types.word, work.cpu_types.address;


and then refer to the used names in declarations:


variable data_word : word;

variable next_address : address;


We can place a use clause in any declarative part in a model.   One way to think

of a use clause is that it imports” the names of the listed items into  the part of  the model containing the use clause.

The syntax rule for a use clause shows that we can write the keyword all instead

of the name of a particular item to import from a package.   This form is very useful,

as  it  is  a  shorthand  way  of  importing  all  of  the  names  defined  in  the  interface  of  a package.   For example, if we are using the IEEE standard-logic package as the basis for the data types in a design, we can import everything from the standard-logic pack- age with a use clause as follows:


use ieee.std_logic_1164.all;


Use clauses may be included at the beginning of a design unit, as well as in de- clarative parts within a design unit.  We have seen earlier how we may include library and use clauses at the head of a design unit, such as an entity interface or architecture body.  This area of a design unit is called its context clause.  The names imported here are made directly visible throughout the design unit.  For example, if we want to use the IEEE standard-logic types in the declaration of an entity, we might write the design unit as follows:


library ieee;  use ieee.std_logic_1164.all;

entity logic_block is

port ( a, b : in std_ulogic;

y, z : out std_ulogic );

end entity logic_block;


The names imported by a use clause in this way are made directly visible in the entire design unit after the use clause.  In addition, if the design unit is a primary unit

(such as an entity declaration or a package declaration), the visibility is extended to any corresponding secondary unit.   Thus, if we include a use clause in the primary unit, we do not need to repeat it in the secondary unit, as the names are automatically visible there.