VHDL Tutorial

VHDL Modelling Concepts
Introduction
Fundamental concepts
Modelling concepts

Elements of behaviour
Elements of structure
Analysis elaboration
Lexical elements
Identifiers
Numbers
Characters and strings 
Syntax descriptions
Constants and variables
Scalar type
Integer types
Floating point types
Time type
Enumeration types
Character types
Boolean type 
Bits type
Standard logic
Sequential statements
Case statements
Loop and exit statements
Assertion statements
Array types & array operations
Architecture bodies
Entity declarations
Behavioral descriptions 
Wait statements
Delta delays
Process statements
Conditional signal assignment 
Selected signal assigment
Structural descriptions
Library and library clauses
Procedures
Procedure parameters
Signal parameters
Default values
Unconstrained array parameter
Functions
Package declarations and bodies
Subprograms in package
Use clauses
Resolved signals and subtypes
Resolved signals and ports
Parameterizing behavior
Parameterizing structure


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VHDL Modeling Concepts

 

In this section, we look at the basic VHDL concepts for behavioral and structural mod- eling.  This will provide a feel for VHDL and a basis from which to work in later chap- ters.    As  an  example,  we  look  at  ways  of  describing  a  four-bit  register,  shown  in Figure 2-1.

Using VHDL terminology, we call the module reg4 a design entity, and the inputs and outputs are ports Figure 2-2 shows a VHDL description of the interface to this entity.  This is an example of an entity declaration.  It introduces a name for the entity and lists the input and output ports, specifying that they carry bit values (0 or 1) into and out of the entity.  From this we see that an entity declaration describes the external view of the entity.

 

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FIGURE 2-1

 

 

reg4

d0       q0

d1       q1

d2       q2

d3       q3

 

en

clk

 

 

 

 

 

 

 

 

 

 

 

 

 

A four-bit register module.  The register is named reg4 and has six inputs, d0, d1, d2, d3, en and clk, and

four outputs, q0, q1, q2 and q3.

 

FIGURE 2-2

 

entity reg4 is

port ( d0, d1, d2, d3, en, clk : in bit;

q0, q1, q2, q3 : oubit );

end entity reg4;

 

 

 

 

 

 

 

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