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VHDL Tutorial |
Wait statements in VHDL | ||
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Introduction Fundamental concepts Modelling concepts Elements of behaviour Elements of structure Analysis elaboration Lexical elements Identifiers Numbers Characters and strings Syntax descriptions Constants and variables Scalar type Integer types Floating point types Time type Enumeration types Character types Boolean type Bits type Standard logic Sequential statements Case statements Loop and exit statements Assertion statements Array types & array operations Architecture bodies Entity declarations Behavioral descriptions Wait statements Delta delays Process statements Conditional signal assignment Selected signal assigment Structural descriptions Library and library clauses Procedures Procedure parameters Signal parameters Default values Unconstrained array parameter Functions Package declarations and bodies Subprograms in package Use clauses Resolved signals and subtypes Resolved signals and ports Parameterizing behavior Parameterizing structure |
Wait Statements
Now that we have seen how to change the values of signals over time, the next step in behavioral modeling is to specify when processes respond to changes in signal val- ues. This is done using wait statements. A wait statement is a sequential statement with the following syntax rule:
wait_statement ⇐ wait [ on signal_name { , … } ] [ until boolean_expression ] [ for time_expression ] ;
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Contact : webmaster@freehost7com The purpose of the wait statement is to cause the process that executes the state- ment to suspend execution. The sensitivity clause, condition clause and timeout clause specify when the process is subsequently to resume execution. We can include any combination of these clauses, or we may omit all three. Let us go through each clause and describe what it specifies. The sensitivity clause, starting with the word on, allows us to specify a list of sig- nals to which the process responds. If we just include a sensitivity clause in a wait statement, the process will resume whenever any one of the listed signals changes value, that is, whenever an event occurs on any of the signals. This style of wait state- ment is useful in a process that models a block of combinatorial logic, since any change on the inputs may result in new output values; for example:
half_add : process is begin sum <= a xor b after T_pd; carry <= a and b after T_pd; wait on a, b; end process half_add;
This form of process is so common in modeling digital systems that VHDL pro- vides the shorthand notation that we have seen in many examples in preceding chap- ters. A process with a sensitivity list in its heading is exactly equivalent to a process with a wait statement at the end, containing a sensitivity clause naming the signals in the sensitivity list. So the half_add process above could be rewritten as
half_add : process (a, b) is begin sum <= a xor b after T_pd; carry <= a and b after T_pd; end process half_add; The condition clause in a wait statement, starting with the word until, allows us to specify a condition that must be true for the process to resume. For example, the wait statement
wait until clk = '1';
causes the executing process to suspend until the value of the signal clk changes to ‘1’. The condition expression is tested while the process is suspended to determine whether to resume the process. If the wait statement doesn’t include a sensitivity clause, the condition is tested whenever an event occurs on any of the signals men- tioned in the condition. If a wait statement includes a sensitivity clause as well as a condition clause, the condition is only tested when an event occurs on any of the signals in the sensitivity clause. For example, if a process suspends on the following wait statement:
wait on clk until reset = '0';
the condition is tested on each change in the value of clk, regardless of any changes on reset. The timeout clause in a wait statement, starting with the word for, allows us to specify a maximum interval of simulation time for which the process should be sus- pended. If we also include a sensitivity or condition clause, these may cause the pro- cess to be resumed earlier. For example, the wait statement
wait until trigger = '1' for 1 ms;
causes the executing process to suspend until trigger changes to ‘1’, or until 1 ms of simulation time has elapsed, whichever comes first. If we just include a timeout clause by itself in a wait statement, the process will suspend for the time given. If we refer back to the syntax rule for a wait statement shown on page 48, we note that it is legal to write
wait;
This form causes the executing process to suspend for the remainder of the simula- tion. We have seen an example of this in test-benches that suspend indefinitely after applying all of the stimuli.
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