VHDL Tutorial Configuration
Introduction to VHDL
History of VHDL
Naming Conventions
Libraries and packages
Entities
Entity Declaration
Entity Example
Ports
Architectures
Architecture declaration
Architecture example
Configurations

Signals
Signal representation
Multivalued logic representation
Built in data types
Synthesis vs simulation
Logical operators
Assignment statements
Process statements
D Flip flop example code
Finite state machine(FSM)
Finite state machine example
Combinational circuit example code
Quad 2 input MUX example
Seven segment display controller
8 Bit register
32 bit counter
 
 
 
 
 

 

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A configuration is a specification of the mapping between an architecture and a particular instance of an entity 

 

   By default, a configuration exists for each entity 

 

   The default configuration maps the most recently compiled architecture to the entity 

 

   Configurations are most often used to specify alternative architectures for hardware designs

 

 

 

 

 

 

 


 

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