VHDLTutorial D flip flop example code
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D Flip flop example code

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Using a process and the EVENT attribute of a signal, it is possible to specify a D flip-flop

 

 

•   The EVENT attribute can be used to check for the rising edge

of a clock signal

 

 

 

•   The block diagram of a D Flip-Flop is shown below:

 

 

 

 

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

 

ENTITY dffe IS

PORT( rst, clk, ena, d : IN std_logic;

q : OUT std_logic ); END dffe;

 

ARCHITECTURE synthesis1 OF dffe IS BEGIN

PROCESS (rst, clk) BEGIN

IF (rst = ‘1’) THEN

q <= ‘0’;

ELSIF (clk’EVENT) AND (clk = ‘1’) THEN IF (ena = ‘1’) THEN

q <= d;

 

END IF; END PROCESS;

END synthesis1;

 

 

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