VHDLTutorial Finite state machine example
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D Flip flop example code
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Finite state machine example

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8 Bit register
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An Example code

 

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;


ENTITY vending IS PORT(
reset : IN std_logic;
clock : IN std_logic;
buttons : IN std_logic_vector(1 DOWNTO 0);
lights : OUT std_logic_vector(1 DOWNTO 0)
);
END vending;
 

ARCHITECTURE synthesis1 OF vending IS
TYPE statetype IS (Idle, Opt1, Opt2, Error); SIGNAL currentstate, nextstate : statetype;
BEGIN
fsm1: PROCESS( buttons, currentstate ) BEGIN
CASE currentstate IS WHEN Idle =>
lights <= “00”; CASE buttons IS
WHEN “00” =>
nextstate <= Idle; WHEN “01” =>
nextstate <= Opt1; WHEN “10” =>
nextstate <= Opt2; WHEN OTHERS =>
nextstate <= Error;
END CASE; WHEN Opt1 =>
lights <= “01”;
IF buttons /= “01” THEN
nextstate <= Idle;
END IF;

WHEN Opt2 =>
lights <= “10”;
IF buttons /= “10” THEN
nextstate <= Idle;
END IF; WHEN Error =>
lights <= “11”;
IF buttons = “00” THEN
nextstate <= Idle;



END CASE; END PROCESS;

END IF;



fsm2: PROCESS( reset, clock )
BEGIN
IF (reset = ‘0’) THEN
currentstate <= Idle;
ELSIF (clock’EVENT) AND (clock = ‘1’) THEN
currentstate <= nextstate;
END IF; END PROCESS;
END synthesis1;
 


 

 


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