| VHDLTutorial | Logical Operators | ||||||||||||
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Introduction to VHDL History of VHDL Naming Conventions Libraries and packages Entities Entity Declaration Entity Example Ports Architectures Architecture declaration Architecture example Configurations Signals Signal representation Multivalued logic representation Built in data types Synthesis vs simulation Logical operators Assignment statements Process statements D Flip flop example code Finite state machine(FSM) Finite state machine example Combinational circuit example code Quad 2 input MUX example Seven segment display controller 8 Bit register 32 bit counter
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VHDL supports the following logical operators:
• VHDL also supports the overloading of existing operators and the creation of new operators using functions
VHDL supports the following relational operators:
= (Equal)
/= (Not Equal)
< (Less Than)
> (Greater Than)
• VHDL supports the following mathematical operators:
+ (Addition)
- (Subtraction)
* (Multiplication)
/ (Division)
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