VHDLTutorial Multivalued logic representation
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MVL (Multi-Valued Logic) representations provide the

additional values necessary to represent high-impedance and unknown signals

 

 

   Two popular multi-valued signal representations are defined

by ieee.std_logic_1164:

 

  MVL - 4

 

  MVL - 9

MVL - 4 adds 2 values (X and Z) to model the state of signals more accurately:

 

 

MVL - 4

Forcing 1

1

Forcing Unknown

X

Forcing 0

0

High Impedance

Z

 

 

 

   Wires can be driven with multiple values

 

 

 

   MVL-4 is rarely used since it still does not provide enough states to model signals accurately

MVL - 9 adds 5 more values to model the state of signals very accurately:

 

 

MVL - 9

Uninitialized

U

Weak 1

H

Dont Care

-

Weak 0

L

Forcing 1

1

Weak Unknown

W

Forcing 0

0

High Impedance

Z

Forcing Unknown

X

 

 

 

  •  Signals can be driven with multiple values

 

  • Signals can be resolved when conflicting values have

 

       been driven

Four standardized types use MVL-9:

 

 

 

Unresolved Types

 

std_ulogic

 

std_ulogic_vector( <max> DOWNT <min>)

 

 

 

Resolved Types

 

std_logic

 

std_logic_vector( <max> DOWNTO <min>  )

 

 

   Resolved types use resolution functions to determine the value on a signal when conflicting values are driven on the signal at the same time

 

 

 

 

 

 

 

 

resolved when conflicting values have been

 

 

 

 

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