VHDL Tutorial Ports
Introduction to VHDL
History of VHDL
Naming Conventions
Libraries and packages
Entities
Entity Declaration
Entity Example
Ports

Architectures
Architecture declaration
Architecture example
Configurations
Signals
Signal representation
Multivalued logic representation
Built in data types
Synthesis vs simulation
Logical operators
Assignment statements
Process statements
D Flip flop example code
Finite state machine(FSM)
Finite state machine example
Combinational circuit example code
Quad 2 input MUX example
Seven segment display controller
8 Bit register
32 bit counter
 
 
 
 
 

 

HOME
 

 

 

 

 


Port name choices:

 

    Consist of letters, digits, and/or underscores

 

    Always begin with a letter       Case insensitive

 

 


 

    Port direction choices:

 

IN        Input port

 

OUT       Output port

 

INOUT     Bidirectional port

 

BUFFER    Buffered output port


 

 

NOTE:                               

  A buffer is an output that can be

read by the architecture of the entity.                                    


 

 

IEEE standard 1164-1993 defines a package which provides a set of data types that are useful for logic synthesis

 

    The external pins of a synthesizable design must use data types specified in the std_logic_1164 package

 

    IEEE recommends the use of the following data types to represent signals in a synthesizable system:

 

std_logic

 

std_logic_vector(<max DOWNTO <min>)

 

 

 

Want To Know more with

Video ???

Contact for more learning: webmaster@freehost7com

 

 


 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Home