VHDL Tutorial Ports
Introduction to VHDL
History of VHDL
Naming Conventions
Libraries and packages
Entity Declaration
Entity Example

Architecture declaration
Architecture example
Signal representation
Multivalued logic representation
Built in data types
Synthesis vs simulation
Logical operators
Assignment statements
Process statements
D Flip flop example code
Finite state machine(FSM)
Finite state machine example
Combinational circuit example code
Quad 2 input MUX example
Seven segment display controller
8 Bit register
32 bit counter







Port name choices:


    Consist of letters, digits, and/or underscores


    Always begin with a letter       Case insensitive




    Port direction choices:


IN        Input port


OUT       Output port


INOUT     Bidirectional port


BUFFER    Buffered output port




  A buffer is an output that can be

read by the architecture of the entity.                                    



IEEE standard 1164-1993 defines a package which provides a set of data types that are useful for logic synthesis


    The external pins of a synthesizable design must use data types specified in the std_logic_1164 package


    IEEE recommends the use of the following data types to represent signals in a synthesizable system:




std_logic_vector(<max DOWNTO <min>)




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