History of VHDL
Naming Conventions
Libraries and packages
Entities
Entity Declaration
Entity Example
Ports
Architectures
Architecture declaration
Architecture example
Configurations
Signals
Signal representation
Multivalued logic representation
Built in data types
Synthesis vs simulation
Logical operators
Assignment statements
Process statements
D Flip flop example code
Finite state machine(FSM)
Finite state machine example
Combinational circuit example code
Quad 2 input MUX example
Seven segment display controller
8 Bit register
32 bit counter
Design a synthesizable VHDL specification of a Seven
Segment Display Controller
• The Seven Segment Display Controller is shown in the system below:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY seven_seg IS
PORT( dataIn : IN std_logic_vector(3 DOWNTO 0);
segments : OUT std_logic_vector(7 DOWNTO 0) ); END seven_seg;
ARCHITECTURE synthesis1 OF seven_seg IS BEGIN
WITH dataIn SELECT
|
segments |
<= |
“10000001” |
WHEN |
“0000”, |
-- |
0 |
|
|
|
“11001111” |
WHEN |
“0001”, |
-- |
1 |
|
|
|
“10010010” |
WHEN |
“0010”, |
-- |
2 |
|
|
|
“10000110” |
WHEN |
“0011”, |
-- |
3 |
|
|
|
“11001100” |
WHEN |
“0100”, |
-- |
4 |
|
|
|
“10100100” |
WHEN |
“0101”, |
-- |
5 |
|
|
|
“10100000” |
WHEN |
“0110”, |
-- |
6 |
|
|
|
“10001111” |
WHEN |
“0111”, |
-- |
7 |
|
|
|
“10000000” |
WHEN |
“1000”, |
-- |
8 |
|
|
|
“10000100” |
WHEN |
“1001”, |
-- |
9 |
|
|
|
“11111111” |
WHEN |
OTHERS; |
|
|
END synthesis1;
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