| VHDLTutorial | Synthesis vs simulation | |||
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Introduction to VHDL History of VHDL Naming Conventions Libraries and packages Entities Entity Declaration Entity Example Ports Architectures Architecture declaration Architecture example Configurations Signals Signal representation Multivalued logic representation Built in data types Synthesis vs simulation Logical operators Assignment statements Process statements D Flip flop example code Finite state machine(FSM) Finite state machine example Combinational circuit example code Quad 2 input MUX example Seven segment display controller 8 Bit register 32 bit counter
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All synthesizable designs can be simulated
• Not all simulation designs can be synthesized
• Consider the following VHDL code: LIBRARY ieee; The input din is assigned to dout after 10 ns
œ Can this represent a real-world system? YES
œ Can this be implemented in a device? PERHAPS
œ Can this be implemented in all devices? NO
• This architecture can be simulated but not synthesized
• Some VHDL design entry tools only permit the use of synthesizable keywords
Most tools understand a synthesizable subset of VHDL93
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